The present invention relates to a semiconductor device. More particularly, the present invention relates to an apparatus for generating a boosting voltage Vpp in a semiconductor device.
Most of semiconductor devices have an internal voltage generator for generating an internal voltage using a power supply voltage Vdd supplied from an outside apparatus in its chip, and supply by itself a voltage needed for operating circuits included in the chip by using the internal voltage generator. A main issue in using the internal voltage generator is to supply stably the internal voltage having a desired level.
However, the power supply voltage Vdd has been rapidly lowered as a scaling-down of critical dimension of an integrated circuit included in a present semiconductor device is continuously progressed. Accordingly, a lay-out technique for satisfying a performance required in a low voltage environment has been required.
In the low voltage environment, most of semiconductor devices use the boosting voltage Vpp having a level higher than the power supply voltage Vdd by a certain level to compensate a voltage loss generated when the semiconductor devices operate using the power supply voltage Vdd and maintain normal data.
The boosting voltage Vpp is frequently employed as a gate voltage of an N-MOS transistor when a core voltage, etc having high level is applied through the N-MOS transistor. Here, the core voltage, etc means a voltage having a level higher than the power supply voltage Vdd of voltages employed in for example, a DRAM.
In addition, since the boosting voltage Vpp is used as a back bias voltage of a P-MOS transistor included in a sense amplifier, the boosting voltage Vpp affects to an operation of the sense amplifier. Accordingly, it is important to maintain stable the boosting voltage Vpp while DRAM is being operated.
FIG. 1A is a view illustrating a control circuit of a common boosting voltage generator. FIG. 1B is a timing diagram illustrating signals used in the control circuit in FIG. 1A. Here, a ractvbp<n> indicates a low pulse generated when nth memory bank is activated, a rpcgbp<n> means a low pulse generated when the nth memory bank is precharged. Additionally, a power up signal pwrup for initializing maintains a low level when a power is turned on, and is converted into high level when the power is stabilized.
According to FIG. 1A, the control circuit of the boosting voltage generator includes P-MOS transistors 10 and 40, an N-MOS transistor 20, a latch circuit 50, inverters 30 and 60, a delay circuit 70 and an NAND gate 80.
According to FIG. 1B, when power is turned on, the P-MOS transistor 40 is instantaneously turned on by the power up signal pwrup. As a result, an output of the latch circuit 50 is reset to low state, i.e. the latch circuit 50 is initialized.
Subsequently, a bank selecting signal ractvbp<n> is generated when a nth memory bank is activated and is converted from high state into low state, and hence an output of the inverter 30 has high level. As a result, the N-MOS transistor 20 is turned on. Hence, a voltage of a node N1 is changed from high state to low state, and so the output of the latch circuit 50 has high state. Accordingly, an output ractb<n> of the inverter 60 has low state, and so an output of the NAND gate 80, i.e. boost voltage pump driving signal vpp_act<n> maintains high state.
Further, a precharge command signal rpcgbp<n> is generated when the nth memory bank is precharged and converted from high state into low state and the P-MOS transistor 10 is turned on. Hence, the voltage of the node N1 is changed from low state into high state, and so the output of the latch circuit 50 has low state. Accordingly, the output ractb<n> of the inverter has high state. That is, the output ractb<n> of the inverter 60 is changed from low state into high state. However, the output of the NAND gate 80 maintains high state during a delay time by the delay circuit 70.
In short, the boost voltage pump driving signal vpp_act maintains high state during the delay time by the delay circuit 70 though the precharge command signal rpcgbp<n> is converted from high state into low state. Hence, a boost voltage pump operates stably.
For the convenience of understanding, it is considered that amount of a boost voltage generated from one boost voltage pump is identical to that of a boost voltage needed for one memory bank for the convenience of description.
In this case, boost voltage pumps correspond one-to-one with memory banks. Hence, when the memory bank is activated, the boost voltage Vpp is uniformly applied to each of the memory banks included in a DRAM.
In case where certain memory bank is activated, a boost voltage pump corresponding to the memory bank is driven. Accordingly, a number of the boost voltage pumps are identical to that of the memory banks.
However, when the number of the memory banks included in the DRAM is great, a number of memory banks activated at a time is limited. For example, in case that 8 memory banks are included in the DRAM, the number of the memory banks may be limited to maximum four.
In this case, though 8 boost voltage pumps corresponding to 8 memory banks are included in the DRAM, only 4 memory banks of the 8 memory banks are activated at a time. In other words, only a half of the boost voltage pumps are operated.
Nevertheless, since each of the memory banks has one boost voltage pump, respectively, the boost voltage pumps are wasted. In addition, the area in Dram corresponding to the boost voltage pumps that are not activated is unnecessarily used.
Specially, since the boost voltage Vpp is higher than the power supply voltage Vdd, a size of the boost voltage pump where a MOS transistor is used as a capacitor is increased. Accordingly, the area which the boost voltage pumps occupy in the DRAM is more augmented.
In other words, the number of the boost voltage pumps effects an area which the control circuit occupies in the DRAM. Accordingly, the constitution of the above boost voltage generator causes increase in the area which the control circuit occupies in the DRAM.